The present invention relates generally to amplifier circuits, and specifically to highly-linear amplifiers.
The need for designing highly-linear amplifiers has become acute during the last decade because of the increasingly precise specifications associated with modern integrated circuits, e.g., wireless equipment and sensitive test equipment. In particular, the suppression of higher-order harmonic distortion in these circuits is desirable, and has been only partially addressed in the prior art through the use of differential circuitry, distortion compensation methods, and deep global feedback.
U.S. Pat. No. 4,267,516 to Traa, U.S. Pat. No. 5,729,176 to Main et al., U.S. Pat. No. 5,126,586 to Gilbert, U.S. Pat. No. 4,287,478 to Berger, U.S. Pat. No. 4,390,848 to Blauschild, and U.S. Pat. No. 4,390,848 to Robert, which are incorporated herein by reference, describe various circuit designs for suppressing odd-order harmonics. In an article by Jensen, et al., entitled, xe2x80x9cA 3.2 GHz Second Order Delta-Sigma Modulator Implemented in InP HBT Technology,xe2x80x9d IEEE Journal of Solid State Circuits, 30(10), October, 1995, which is incorporated herein by reference, a technique for compensating for odd-order harmonics is described.
These circuits provided by the prior art, although improving linearity, leave several issues unresolved which prevent achieving the linearity required by state-of-the-art specifications. First, even if a circuit is theoretically designed to be symmetric, in practice there are always asymmetries, caused by variations in manufacturing processes, which result in the appearance of even-order harmonics in the output spectrum of a circuit. Second, in the existing designs of compensation circuits, the amplitude and phase balance at higher frequencies is violated, and the desired compensation is consequently not achieved.
Reference is now made to FIGS. 1, 2A, 2B, and 2C. FIG. 1 is a schematic diagram of a prior art bipolar linear amplifier 20, as depicted in the above-cited article by Jensen. This amplifier includes three blocks: a differential pair block 30, a current-voltage block 40, and an odd-order harmonic correction block 50, shown respectively in FIGS. 2A, 2B, and 2C.
Block 30 (FIG. 2A) forms the basis of prior art amplifier 20. It includes transistors Q1 and Q2, and a resistor R1, configured to form a first differential pair. The function of block 30 is to convert an input voltage signal VIN applied to the bases of the transistors into a nonlinear current I flowing through Q1 and Q2.
Block 40 (FIG. 2B) includes transistors Q6 and Q7 in a common base structure. The emitters of Q6 and Q7 are connected to the collectors of transistors Q1 and Q2, respectively. The function of block 40 is to convert the nonlinear collector currents of Q1 and Q2 into nonlinear voltages, which are applied as inputs to block 50, and to bypass the collector currents of Q6 and Q7 to the output of amplifier 20.
Block 50 (FIG. 2C) of prior art amplifier 20 is a compensation circuit for odd-order harmonics. Block 50 includes a second differential pair, consisting of transistors Q8 and Q9, and a resistor R2. The bases of transistors Q8 and Q9 are respectively connected to the emitters of transistors Q6 and Q7, and the collectors of transistors Q8 and Q9 are cross-connected to the output of the amplifier. The purpose of block 50 is to convert voltages appearing at the bases of Q8 and Q9 into currents equal to the nonlinear parts of the collector currents of Q1 and Q2. The cancellation of odd-order harmonics is then achieved by cross-connecting of the collectors of Q8 and Q9 to the collectors of Q6 and Q7, as shown in FIG. 1. The structure of amplifier 20, however, does not provide cancellation of even-order harmonics.
Preferred embodiments of the present invention provide an improved amplifier circuit, preferably a bipolar linear amplifier, in which second- and third-order harmonics are simultaneously suppressed. The amplifier comprises a main gain unit and a harmonic compensation circuit that remains effective over a range of frequencies and which provides output linearity that generally has low sensitivity to variations in manufacturing processes of the circuit elements. As a result, the amplifier has increased linearity over wider bandwidth than comparable devices known in the art.
In preferred embodiments of the present invention, the linear amplifier comprises an odd order compensation circuit and an even order compensation circuit. These circuits are preferably optimized for the design frequency of the amplifier. Most preferably, the amplifier further comprises a linear phase matching filter, for increasing the effective bandwidth of the compensation circuits.
There is therefore provided, in accordance with a preferred embodiment of the present invention, a differential linear amplifier having an input and an output, including:
a main differential amplification circuit, coupled to receive a differential input signal at the input of the amplifier and to generate a differential output signal at the output of the amplifier;
an odd-order compensation circuit, coupled to sample an odd-order harmonic current in the main differential amplification circuit and to amplify the sampled odd-order harmonic current so as to generate an odd-order compensation signal for subtraction from the differential output signal; and
an even-order compensation circuit, coupled to sample an even-order harmonic current in the main differential amplification circuit and to amplify the sampled even-order harmonic current so as to generate an even-order compensation signal for subtraction from the differential output signal.
In a preferred embodiment, the differential input signal includes an input voltage signal, and the main differential amplification circuit includes a transconductance cell, which is adapted to generate the differential output signal in the form of an output voltage or current signal.
Preferably, the main differential amplification circuit includes a differential pair of transistors mutually connected by a lattice of resistors, the lattice having first and second intermediate nodes, wherein the resistors are arranged to cancel the odd-order harmonic current at the first and second intermediate nodes, and wherein the even-order compensation circuit has first and second inputs that are respectively coupled to the first and second intermediate nodes so as to sample the even-order harmonic current. Most preferably, the even-order compensation circuit includes a pair of transistors, which are coupled respectively to the first and second differential inputs of the even-order compensation circuit, and which are mutually linked by a biasing circuit having a resistance chosen so that the even-order compensation signal cancels a second-order harmonic component in the differential output signal.
Preferably, the amplifier includes a filter, coupled to the output of the amplifier between the main differential amplification circuit and the odd-order compensation circuit, so as to provide phase matching of a third-order harmonic component at a desired frequency at the output of the amplifier between the differential output signal generated by the main differential amplification circuit and the odd-order compensation signal. Most preferably, the filter includes a second-order linear filter. Additionally or alternatively, the filter is further coupled between the main differential amplification circuit and the even-order compensation circuit, so as to provide phase matching of a second-order harmonic component at the desired frequency at the output of the amplifier between the differential output signal generated by the main differential amplification circuit and the even-order compensation signal.
There is also provided, in accordance with a preferred embodiment of the present invention, a differential linear amplifier having an input and an output, including:
a main differential amplification circuit, including:
a first differential pair of transistors arranged to amplify a differential input signal that is input to the amplifier so as to generate a differential output signal at the output of the amplifier, the transistors including respective bases that are coupled to receive the input signal and respective collectors and respective emitters;
at least one first resistor, having an effective resistance R1, connected between the emitters; and
a second differential pair of transistors coupled together in a common-base structure and including emitters coupled respectively to the collectors of the transistors in the first differential pair and collectors coupled to the output of the amplifier; and an odd-order compensation circuit, including:
a third differential pair of transistors including respective bases that are coupled respectively to the collectors of the first differential pair of transistors and respective collectors that are coupled to the output of the amplifier so as to generate a harmonic compensation signal at the output of the amplifier, and further including respective emitters; and
at least one second resistor, having an effective resistance R2, connected between the emitters of the third differential pair of transistors,
wherein the resistances R1 and R2 are given substantially by:                     r        1            ⁡              (                              r            2                    ,          m                )              =          2      ·                                    m            ·                                          (                                  1                  +                                      0.5                    ·                                          r                      2                                                                      )                            4                                +                      (                          1              -              m                        )                                                (                          1              -              m                        )                    ·                      [                                                            (                                      1                    +                                          0.5                      ·                                              r                        2                                                                              )                                3                            -              1                        ]                                ,
wherein             r      i        =                  R        i            ·              I        i            ·              q                  k          ·          T                      ,
xe2x80x83for an index       i    =    1    ,  2  ,                    I        1                    I        2              =          m              1        -        m            
xe2x80x83m a parameter such that 0 less than m less than 1, I1 is a DC bias current of the transistors in the first differential pair, I2 is a DC bias current of the transistors in the third differential pair, q is a unit of elementary charge, k is Boltzmann""s constant, and T is an operating temperature of the transistors.
Preferably, the amplifier includes a filter, coupled to the output of the amplifier between the main differential amplification circuit and the odd-order compensation circuit, so as to provide phase matching of a third-order harmonic component at a desired frequency at the output of the amplifier between the differential output signal generated by the main differential amplification circuit and the odd-order compensation signal.
There is additionally provided, in accordance with a preferred embodiment of the present invention, a method for linearizing an amplifier, including:
coupling a main differential amplification circuit to receive a differential input signal at an input of the amplifier and to generate a differential output signal at an output of the amplifier;
sampling an odd-order harmonic current in the main differential amplification circuit
amplifying and phase-matching the sampled odd-order harmonic current in an odd-order compensation circuit so as to generate an odd-order compensation signal
sampling an even-order harmonic current in the main differential amplification circuit;
amplifying and phase-matching the sampled even-order harmonic current in an even-order compensation circuit so as to generate an even-order compensation signal; and
subtracting the phase-matched odd-order and even-order compensation signals from the differential output signal.
There is further provided, in accordance with a preferred embodiment of the present invention, a method for linearizing a differential amplifier having an input and an output, including:
providing a main differential amplification circuit, including:
a first differential pair of transistors arranged to amplify a differential input signal that is input to the amplifier so as to generate a differential output signal at the output of the amplifier, the transistors including respective bases that are coupled to receive the input signal and respective collectors and emitters;
at least one first resistor, having an effective resistance R1, connected between the emitters; and
a second differential pair of transistors coupled together in a common-base structure and including emitters coupled respectively to the collectors of the transistors in the first differential pair and collectors coupled to the output of the amplifier;
providing an odd-order compensation circuit, including:
a third differential pair of transistors including respective bases that are coupled respectively to the collectors of the first differential pair of transistors and respective collectors that are coupled to the output of the amplifier so as to generate a harmonic compensation signal at the output of the amplifier, and further including respective emitters; and
at least one second resistor, having an effective resistance R2, connected between the emitters of the third differential pair of transistors; and
setting the resistances R1 and R2 so that the resistances are given substantially by:                     r        1            ⁡              (                              r            2                    ,          m                )              =          2      ·                                    m            ·                                          (                                  1                  +                                      0.5                    ·                                          r                      2                                                                      )                            4                                +                      (                          1              -              m                        )                                                (                          1              -              m                        )                    ·                      [                                                            (                                      1                    +                                          0.5                      ·                                              r                        2                                                                              )                                3                            -              1                        ]                                ,
wherein             r      i        =                  R        i            ·              I        i            ·              q                  k          ·          T                      ,
xe2x80x83for an index       i    =    1    ,  2  ,                    I        1                    I        2              =          m              1        -        m            
xe2x80x83m, a parameter such that 0 less than m less than 1, I1 is a DC bias current of the transistors in the first differential pair, I2 is a DC bias current of the transistors in the third differential pair, q is a unit of elementary charge, k is Boltzmann""s constant, and T is an operating temperature of the transistors.
The present invention will be more fully understood from the following detailed description of the preferred embodiments thereof, taken together with the drawings, in which: